To increase their speed of operation, devices are continuously scaled. For example, channel lengths of floating gate based non volatile memory devices are decreased. Because programming voltages remain unchanged, short channel behaviors become problematic during programming when the channel lengths decrease. Typically, to program a selected device, a high drain voltage (Vd) is applied to the bit line of the selected device and a gate voltage (Vg) is applied to a word lines. Since other devices that are not to be programmed (unselected devices) are also coupled to the bit line of the selected device but the word line they are coupled to has a Vg of zero, the unselected devices experience Drain Induced Barrier Lowering (DIBL). DIBL lowers the threshold voltage (Vt) of the unselected devices and introduces high column leakage during programming in which a high Vd is applied to the selected bit line.
In addition, when on volatile memory devices are scaled the thickness of a tunnel oxide is decreased. This decrease in oxide thickness increases read disturb or Low Temperature Date Retention (LTDR) from a low Vt state. One solution to reduce LTDR is to reduce the natural ultraviolet Vt of the device. However, the short channel effects, such as DIBL are more severe when the natural ultraviolet Vt is decreased. Thus, column leakage becomes larger, which negatively impacts programming efficiency and time.
Thus, a need exists for a programming scheme that reduces LTDR and does not decrease programming efficiency.
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